1. Field of the Invention
The present invention relates to a self-repair method for nonvolatile memory devices using a supersecure architecture, and a nonvolatile memory device.
2. Description of the Related Art
As is known, in a semiconductor multimegabit nonvolatile memory device (EPROM or flash), the cell array occupy a substantial fraction, accounting for between 40% and 70% of the total area. The applications for which nonvolatile memories are designed impose the need for perfect functionality of all the cells in the array during the operation of the device (reading, programming and erasing).
In theory, the presence of at least one cell that does not operate correctly is sufficient for the entire memory device to be unusable. This condition is of considerable importance during the process of industrial fabrication of this type of integrated device, in so far as there exists a non-zero likelihood of failure of a memory cell in any given production lot.
In the absence of solutions for detecting and correcting failure bits, the likelihood of having devices with perfectly operating memory cells in a given production lot would be very low and hence unacceptable from the point of view of large-scale industrial production. This value indicates the so-called “prime yield” of the lot and represents a figure of merit of the production process.
In order to increase the yield of memory devices in the final production steps, circuit solutions have been employed for recognizing and correcting the failure bits. A technique commonly adopted for this purpose uses additional memory cells to those making up the memory array and designed to replace corresponding failed array cells. The cells used, defined as redundant cells or redundancy cells, are identical to the array cells. They must be appropriately managed by additional circuits to those already normally present inside the device.
In particular, the organization of the memory favors the use of entire rows or entire columns made up of redundant cells, such as to replace corresponding rows or columns of the array even in the presence of just one failed cell. In this way, a compromise is reached between the power for correcting the failures and the area required for the circuits managing the redundancy.
Usually, activation of redundancy occurs during the electrical wafer sorting (EWS) step, during which, using an appropriate test flow, the cells that present some problems are identified and replaced with the redundancy cells. The redundancy, whether row redundancy or column redundancy, is thus able to correct only the defects that occur at time zero, i.e., in the factory.
For instance, should a sensible reduction in gain arise for a given cell, on account of cycling, the cell could no longer be able to get over the erasing and programming steps, so causing breakdown of the entire device.
Such an occurrence is increasingly frequent in the case of memories that use a long internal word, for example, a 64-bit or 128-bit word, as frequently occurs in present memories, in particular in the case of multilevel nonvolatile memories, where a number of bits are stored per cell, and in the case of memories with synchronous (burst) reading.
In fact, in the case of multilevel memories, where the difference in the threshold voltages between the different levels is reduced and thus a very precise control is required on the stored charge, it is advantageous, during programming, to apply a linearly increasing staircase voltage. Programming, however, becomes slow, so that in order to obtain a programming time of a single byte comparable to that of a conventional two-level cell, it is necessary to program more cells in parallel.
In addition, in the case of synchronous reading, the data are outputted in a synchronous manner, being controlled by an external clock. The frequency of the clock is, in general, higher than that of the asynchronous access time. Consequently, it is necessary to read a very much longer binary word internally than the one that is supplied at output in order to have a reserve from which it is possible to draw for different clock periods.